Section: New Results

Data-Aware Process Networks

Participants : Christophe Alias, Alexandru Plesco [XtremLogic start-up] .

Process networks are execution models expressing naturally the parallelism of a computation. They are a natural intermediate representation for high-level synthesis tools, where the front-end extracts the parallelism and produces a process network and the back-end compiles the process network to the target architecture.

In that context, we have defined a new model of process network that fits HLS-specific constraints, the data-aware process network (DPN). Our model makes explicit the communications with the central memory and the parallel access to channels, and is close enough to the hardware constraints to be translated directly to a circuit. We show how to compile an imperative program to a DPN, so as to optimize both the I/O and the parallelism, while using the polyhedral model.

DPNs are used as the intermediate representation for the HLS compiler suite of the XtremLogic start-up. They are generated from C programs by the Dcc compiler (see Section  5.5 ). The apparatus underlying the DPN synchronizations has been patented by Inria [12] .